Travel Schedule
I am currently on the job market with graduation planned in the Summer of 2010. If you would like to talk to me I will be traveling to:
FusionIO - Salt Lake City, UT - March 8th
Intel - Santa Clara, CA - March 10th
ASPLOS - Pittsburgh, PA - March 13-17th
Lake Forest College - Lake Forest, IL - March 18-21st
University of Pennsylvania - Philadelphia, PA - March 25th
ISPASS - White Plains, NY - March 29-30th
Research Interests
Computer Architecture, Operating Systems, High Performance Computing, Very Large Data Sets, Asynchronous Systems, Quantitative Finance and Signal Processing
Education
- PhD Candidate in Computer Science - Expected Summer 2010
University of Utah. Salt Lake City, UT
Advisors: Dr. Erik Brunvand and Dr. Rajeev Balasubramonian - B.A. in Computer Science with High Honors - May 2002
Colgate University. Hamilton, NY
Advisor: Dr. Chris Nevison
Refereed Conference and Journal Publications
- Improving Server Performance on Multi-Cores via Selective Off-loading of OS Functionality - Available on Request
David Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian, Under Review, January 2009 - ABP: Predictor-Based Management of DRAM Row-Buffers in the Many-Core Era - Available on Request
Manu Awasthi, David Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis, Under Review, November 2009 - SWEL: Hardware Cache Coherence Protocols to Map Shared Data onto Shared Caches - Available on Request
Seth H. Pugsley, Josef Spjut, David Nellans, Rajeev Balasubramonian, Under Review, November 2009 - Leveraging OS-User Virtual Threads In Private Caches - Available on Request
David Nellans, Kshitij Sudan, Manu Awasthi, Erik Brunvand, Rajeev Balasubramonian, Under Review, November 2009 - Hardware Prediction of OS Run-Length For Fine-Grained Resource Customization
David Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian, ISPASS, March 2010 - Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement
Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis, ASPLOS XV, March 2010 - OS Execution on Multi-Cores: Is Out-Sourcing Worthwhile?
David Nellans, Rajeev Balasubramonian, and Erik Brunvand, Operating Systems Review 43:2, Special Issue on Interaction of Operating Systems and Multicore Chips, April 2009 - A Case For Increased Operating System Support in Chip Multi-Processors
David Nellans, Rajeev Balasubramonian, and Erik Brunvand, 2nd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2), September 2005 - ARCS: An Asynchronous Architectural Level Simulator
David Nellans, Vamshi Krishna Kadaru, and Erik Brunvand, Great Lakes Symposium on VLSI (GLSVLSI), April 2004 - Communicating Sequential Process In Java: Simplified Distributed Computing
David Nellans and Chris Nevison, National Conference on Undergraduate Research, May 2002 - Algorithms For Finding Small Dominating Sets
David Nellans and Laura Sanchis, National Conference on Undergraduate Research, May 2001
Non-Refereed Publications
- Interference Aware Cache Designs for Operating System Execution
David Nellans, Rajeev Balasubramonian, and Erik Brunvand, University of Utah School of Computing Technical Report UUCS-09-002, February 2009 - BBCSP: A Distributed Branch and Bound Framework Within Java
David Nellans, Colgate University Invited High Honors Thesis, May 2002
Research and Professional Experience
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University of Utah - Graduate Research Assistant. Summer 2002 to Present
- Dissertation Research - Focused on increasing operating system support in future chip multi-processors. Developing hardware innovations that can selectively isolate the OS from user execution at runtime, resulting in improved performance and power efficiency for server applications. Advisors: Dr. Erik Brunvand, Dr. Rajeev Balasubramonian
- Other Architecture Research - Memory subsystem optimization including OS/Hardware interaction in regards to virtual/physical page layout in DRAM, memory controller policies, and multiple memory controller interaction. Cache coherence protocols that map shared data onto shared hardware resources in chip multi-processors to reduce protocol complexity and implementation overhead.
- Other Research - Collaboration with Dr. Kimble Frazer, U. of Utah Huntsman Cancer Institute, to determine relationship between DNA methylation and T-Cell leukemia via statistical datamining of the zebrafish genome. Received Utah Undergraduate Research Opportunities Program (UROP) grant of $1,200 to fund and advise undergraduate student researcher as part of project.
- Common Futures Research - Owner. 2003 to Present
Manage a business that acquires, rehabs, and provides high quality, safe and secure living environments. Our focus group are families in the Salt Lake Valley area who might otherwise not be able to qualify for similar situations without assistance. - Prediction Company - Systems Developer. 2006-2008
Developer creating systems that performed fully automated quantitative trading of US equities and treasuries. Work included bringing on-line a trading product for a new asset class including real time data collection, signal generation, order execution, and back end accounting. Developed a framework for automated data mining and back-testing potential signals using non-linear optimization. Worked with a small team including the CTO to rewrite both research and production data environments to allow high performance access to data sources exceeding 1TB in size. Mentor: Jim Nusbaum (CTO) - Intel Research - Graduate Research Intern. Summer 2006
Researcher in Intel's F.A.C.T research group investigating the use of hardware performance counters to perform statistical analysis of hardware utilization. Real-time performance analysis is used to improve operating system scheduling algorithms for both performance and energy effciency, as well as tracking the soft error rates of a microprocessor. Mentor: Dr. Athanasios Papathanasiou - Sun Microsystems Laboratories - Graduate Research Intern. Summer 2004
Sun Microsystems Laboratories - Graduate Research Intern. Summer 2004 Researcher in Sun Labs' asynchronous circuits group investigating a novel computer architecture utilizing the GasP family of asynchronous control circuits. Investigation into using these circuits to form a high speed FLEET switching network as an on chip interconnect between micro-architectural structures. Work involved designing and simulating a latency tolerant, general purpose architecture that leveraged the advantages of an extremely fast switching interconnect. Micro-architecture focused on data movement, not computation, as the fundamental programming model. Mentor: Dr. Ivan Sutherland - Colgate University - Undergraduate Research Assistant. Summers 1999, 2000, 2001
Variety of research into areas of NP-Complete approximation algorithms, communicating sequential processes (CSP) over TCP/IP, and provably correct distributed computing algorithms. Advisor: Dr. Chris Nevison. Mentors: Dr. Laura Sanchis, Dr. Rod Moten
Teaching Experience
- University of Utah. Fall 2009
Designed and taught a new special topics course with enrollment of 20 students, titled "Software Engineering For Very Large Data Sets", and targeted at senior year undergraduates. Project based course covered the practical aspects of storing, accessing, and computing on data sets that are terabyte and larger in size. Topics included row vs. column oriented database models, distributed systems, and parallel programming across commodity clusters. Received hardware grants from Sun Microsystems (T5220 Server - $32,000) and FusionIO (IODrive 160GB - $7,000) for large database performance exploration. - University of Utah. Fall 2009
Guest lecturer for undergraduate course on C programming for non-majors. - University of Utah. Spring 2009
Teaching assistant for advanced graduate course on memory system design. - University of Utah. Fall 2002
Teaching assistant and guest lecturer for undergraduate computer architecture course. - Colgate University. 1999-2002
Teaching assistant for seven different undergraduate computer science courses including introduction to programming, functional programming, computer architecture, set theory, and multiple advanced topics. - Tesuque Pueblo. Fall 2001
Taught a combined fifth and sixth grade class three days a week on basic computer proficiency. - Johns Hopkins Center for Talent Youth. Summer 2001
Teaching assistant in both a classroom and laboratory setting instructing exceptional 13 to 16 year old students. Shared responsibility for planning and delivering college level computer science course material, assessing student progress, and judging future capabilities in computer science. - Colgate University Advanced Placement Computer Science Workshop. Summer 2000
Teaching assistant at a week long workshop for high school teachers on the AP computer science curriculum. Helped teachers understand and be able to deliver effective instruction on the new case study used by the AP exam.
Honors and Awards
- Colgate University Award for Excellence in Research, 2002
- Colgate University High Honors In Computer Science, 2002
- Colgate University Award for Outstanding Contribution To Computer Science, 2002
- Association for Computing Machinery (ACM) Syracuse Chapter, Four Year Award, 2001
- Upsilon Pi Epsilon National Undergraduate Computing Honor Society, 2001
Service and Activities
- Web chair for 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI). Fall 2009
- Technical reviewer for ASYNC '03 - '05, HiPC '08 - '09, PPoPP '10, ISCA '10, IEEE Transactions on Computers
- Instructor at U. of Utah Alternative Energy Summer Camp for high school students. Summer 2009
- Research Day Poster Competitions. University of Utah, School of Computing. '05, '09 (runner up)
- Santa Fe High School Varsity Soccer Coach. Fall 2007
- Graduate student advisory committee. University of Utah, School of Computing. '03-'04
- Technology consultant for Santa Clara Pueblo Tribal Offices. Fall 2001
- Member ACM, IEEE, SIGARCH, SIGMICRO
Last Updated: January 15th, 2010
Focused Resume, References, or PDF Version Available Upon Request